kvr13lr9s8/4 4gb 1rx8 512m x 72-bit pc3l-10600 cl9 registered w/parity 240-pin dimm description this document describes valueram's 512m x 72-bit (4gb) ddr3l-1333 cl9 sdram (synchronous dram), low voltage, registered w/parity, 1rx8 ecc, memory module, based on nine 512m x 8-bit ddr3l-1333 fbga components. the spd is programmed to jedec standard latency ddr3-1333 timing of 9-9-9 at 1.35v and 1.5v. this 240-pin dimm uses gold contact fingers. the electrical and mechanical specifications are as follows: features ? jedec standard 1.35v (1.28v ~ 1.45v) and 1.5v (1.425v ~ 1.575v) power supply ? vddq = 1.35v (1.28v ~ 1.45v) and 1.5v (1.425v ~ 1.575v) ? 667mhz fck for 1333mb/sec/pin ? 8 independent internal bank ? programmable cas latency: 9, 8, 7, 6 ? programmable additive latency: 0, cl - 2, or cl - 1 clock ? programmable cas write latency(cwl) = 7 (ddr3-1333) ? 8-bit pre-fetch ? burst length: 8 (interleave without any limit, sequential with starting address ?000? only), 4 with tccd = 4 which does not allow seamless read or write [either on the fly using a12 or mrs] ? bi-directional differential data strobe ? internal(self) calibration : internal self calibration through zq pin (rzq : 240 ohm 1%) ? on die termination using odt pin ? on-dimm thermal sensor (grade b) ? average refresh period 7.8us at lower than tcase 85c, 3.9us at 85c < tcase < 95c ? asynchronous reset ? pcb : height 1.180? (30.00mm), double sided component document no. valueram1326-001.b00 10/10/14 page 1 memory module speci cations specifications 9 ) d d i ( l c cycles row cycle time (trcmin) 49.5ns (min.) refresh to active/refresh 260ns (min.) command time (trfcmin) row active time (trasmin) 36ns (min.) maximum operating power (1.35v) = 2.374 w* (1.50v) = 2.728 w* 0 - v 4 9 g n i t a r l u operating temperature 0 o c to 85 o c storage temperature -55 o c to +100 o c *power will vary depending on the sdram and register/pll used. continued >>
module dimensions: document no. valueram1326-001.b00 page 2
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